Monte Carlo Fan Company MC49-L series Spécifications

Intel® 810E2 Chipset Platform Design Guide August 2002 Document Number: 298248-002R

Intel® 810E2 Chipset Platform R 10 Design Guide Tables Table 1. Platform Pin Definition Comparison for Single Processor Designs ...

Intel® 810E2 Chipset Platform R 100 Design Guide 3.23. FWH Decoupling A 0.1 µF capacitor should be placed between the Vcc supply pins and the V

Intel® 810E2 Chipset Platform R Design Guide 101 The filter specification is graphically shown in the following figure. Figure 61. Filter Spe

Intel® 810E2 Chipset Platform R 102 Design Guide 3.24.4. Recommendation for Intel® Platforms The following tables are examples of components t

Intel® 810E2 Chipset Platform R Design Guide 103 Figure 62. Using Discrete R v005LC<0.1 ohm routePLL2PLL1370-PinSocket<0.1 ohm routeRVCCC

Intel® 810E2 Chipset Platform R 104 Design Guide 3.24.5. Custom Solutions As long as filter performance as specified in the previous “Filter Sp

Intel® 810E2 Chipset Platform R Design Guide 105 3.25. RAMDAC/Display Interface The following figure shows the interface of the RAMDAC analog c

Intel® 810E2 Chipset Platform R 106 Design Guide In addition to the termination resistance and LC pi-filter, there are protection diodes connec

Intel® 810E2 Chipset Platform R Design Guide 107 Figure 66. RAMDAC Component and Routing Guidelines RAMDACVCCDACA1/VCCDACA2VCCDAREDGraphicsCh

Intel® 810E2 Chipset Platform R 108 Design Guide The following figure shows the recommended reference resistor placement and connections. Fig

Intel® 810E2 Chipset Platform R Design Guide 109 Figure 68. Recommended LC Filter Connection RVCCDADisplay PLL and RAMDAClc_filter.vsdVCCDACA

Intel® 810E2 Chipset Platform R Design Guide 11 Table 51. Flexible Motherboard Processor System Bus AC Guidelines (Clock) at the Processor Pins

Intel® 810E2 Chipset Platform R 110 Design Guide the filter characteristics. This resistance includes the routing resistance from the board pow

Intel® 810E2 Chipset Platform R Design Guide 111 Table 29. Additional DPLL LC Filter Component Example Component Manufacturer Part No. Desc

Intel® 810E2 Chipset Platform R 112 Design Guide Table 30. Resistance Values for Frequency Response Curves Curve RTRACE + RDISCRETE RIND 0 2.

Intel® 810E2 Chipset Platform R Design Guide 113 4. Advanced System Bus Design This chapter discusses more detail about the methodology used t

Intel® 810E2 Chipset Platform R 114 Design Guide 4.1.1. Initial Timing Analysis Perform an initial timing analysis of the system using the Set

Intel® 810E2 Chipset Platform R Design Guide 115 There are multiple cases to consider. Note that while the same trace connects two components,

Intel® 810E2 Chipset Platform R 116 Design Guide Table 32 and Table 33 are derived assuming: • CLKSKEW = 0.2 ns (Note: Assumes clock driver pi

Intel® 810E2 Chipset Platform R Design Guide 117 4.1.2. Determine General Topology, Layout, and Routing Desired After calculating the timing b

Intel® 810E2 Chipset Platform R 118 Design Guide 4.1.3.3. Monte Carlo Analysis Perform a Monte Carlo analysis to refine the passing solution s

Intel® 810E2 Chipset Platform R Design Guide 119 The transmission line package models must be inserted between the output of the buffer and the

Intel® 810E2 Chipset Platform R 12 Design Guide Revision History Rev. Description Date -001 • Initial Release January 2001 -002 • Replac

Intel® 810E2 Chipset Platform R 120 Design Guide Table 34 contains the trace width:space ratios assumed for this topology. The crosstalk cases

Intel® 810E2 Chipset Platform R Design Guide 121 4.1.5.1. Intersymbol Interference Intersymbol Interference (ISI) refers to the distortion or c

Intel® 810E2 Chipset Platform R 122 Design Guide 4.1.6.2. Flight Time Simulation As defined in Chapter 1, flight time is the time difference b

Intel® 810E2 Chipset Platform R Design Guide 123 4.1.6.3. Flight Time Hardware Validation When a measurement is made on the actual system, TCO

Intel® 810E2 Chipset Platform R 124 Design Guide 4.2.3. Crosstalk Theory AGTL+ signals swing across a smaller voltage range and have a correspo

Intel® 810E2 Chipset Platform R Design Guide 125 Additional aggressors are possible in the z-direction, if adjacent signal layers are not route

Intel® 810E2 Chipset Platform R 126 Design Guide Intrinsic Impedance ZLC000=(Ω) Stripline Intrinsic Propagation Speed SSTRIPLINEr01017_.*=ε(n

Intel® 810E2 Chipset Platform R Design Guide 127 4.3.2. Effective Impedance and Tolerance/Variation The impedance of the PCB needs to be contr

Intel® 810E2 Chipset Platform R 128 Design Guide When it is not possible to route the entire AGTL+ signal on a single VSS referenced layer, the

Intel® 810E2 Chipset Platform R Design Guide 129 Figure 77. One Layer with Multiple Reference Planes 1lay_Mult_refplane.vsdGroundSignal Layer A

Intel® 810E2 Chipset Platform R Design Guide 13 1. Introduction This design guide provides motherboard design guidelines for Intel® 810E2 chips

Intel® 810E2 Chipset Platform R 130 Design Guide 4.3.4. Clock Routing Analog simulations are required to ensure clock net signal quality and sk

Intel® 810E2 Chipset Platform R Design Guide 131 4.4.1. VREF Guardband To account for noise sources that may affect the way an AGTL+ signal bec

Intel® 810E2 Chipset Platform R 132 Design Guide 4.4.4. Flight Time Definition and Measurement Timing measurements consist of minimum and maxi

Intel® 810E2 Chipset Platform R Design Guide 133 5. Clocking 5.1. Clock Generation There is only one clock generator component required in an 8

Intel® 810E2 Chipset Platform R 134 Design Guide Features (56 Pin SSOP Package) • 3 copies of processor clock 66/100/133 MHz (2.5V) (Processor

Intel® 810E2 Chipset Platform R Design Guide 135 5.2. Clock Architecture Figure 80. Intel® 810E2 Chipset Clock Architecture clk_arch.vsd5255504

Intel® 810E2 Chipset Platform R 136 Design Guide 5.3. Clock Routing Guidelines The following table shows the group skew and jitter limits.

Intel® 810E2 Chipset Platform R Design Guide 137 Table 39. Layout Dimensions Group Receiver Resistor Cap Topology A B C D MCLK DIMM 22 Ω N/A

Intel® 810E2 Chipset Platform R 138 Design Guide Figure 81. Different Topologies for the Clock Routing Guidelines Layout 1BA Layout 2BCABD La

Intel® 810E2 Chipset Platform R Design Guide 139 5.4. Capacitor Sites Intel recommends 0603 package capacitor sites placed as close as possible

Intel® 810E2 Chipset Platform R 14 Design Guide Term Definition Suspend-To-RAM (STR) In the STR state, the system state is stored in main

Intel® 810E2 Chipset Platform R 140 Design Guide 5.5. Clock Power Decoupling Guidelines Several general layout guidelines should be followed w

Intel® 810E2 Chipset Platform R Design Guide 141 Figure 83. Example of Clock Power Plane Splits and Decoupling

Intel® 810E2 Chipset Platform R 142 Design Guide 5.6. Clock Skew Requirements To ensure correct system functionality, certain clocks must main

Intel® 810E2 Chipset Platform R Design Guide 143 6. Power Delivery The following figure shows the power delivery architecture for an example 81

Intel® 810E2 Chipset Platform R 144 Design Guide Figure 84. Power Delivery Map Intel® 810E2 Chipset UniversalSocket 370 PlatformPower MapVRM8

Intel® 810E2 Chipset Platform R Design Guide 145 Figure 85. G3-S0 Transistion Clocks invalid Clocks validt17t16t15t14t13t12t10t11t9t8t7t6t5t4t3

Intel® 810E2 Chipset Platform R 146 Design Guide Figure 86. S0-S3-S0 Transition DRAM activeDRAM in STR (CKE low) DRAM activeClocks valid Cloc

Intel® 810E2 Chipset Platform R Design Guide 147 Figure 87. S0-S5-S0 Transition DRAM activeDRAM in STR (CKE low) DRAM activeClocks valid Cloc

Intel® 810E2 Chipset Platform R 148 Design Guide Table 41. Power Sequencing Timing Definitions Symbol Parameter Min. Max. Units t1 VccSUS good

Intel® 810E2 Chipset Platform R Design Guide 149 6.2. Pull-up and Pull-down Resistor Values The pull-up and pull-down values are system depend

Intel® 810E2 Chipset Platform R Design Guide 15 Term Definition Crosstalk The reception on a victim network of a signal imposed by aggresso

Intel® 810E2 Chipset Platform R 150 Design Guide 6.3. ATX Power Supply PWRGOOD Requirements The PWROK signal must be glitch free for proper po

Intel® 810E2 Chipset Platform R Design Guide 151 6.4.1. Power Button Implementation The following items should be considered when implementing

Intel® 810E2 Chipset Platform R 152 Design Guide 6.4.2. 1.8V / 3.3V Power Sequencing The ICH2 has two pairs of associated 1.8V and 3.3V suppli

Intel® 810E2 Chipset Platform R Design Guide 153 If one of these signals goes high while one of its associated power planes is active and the o

Intel® 810E2 Chipset Platform R 154 Design Guide 6.4.4. GMCH Decoupling Guidelines GMCH Vsus 3.3V (3.3V Standby) Power Plane Decoupling The us

Intel® 810E2 Chipset Platform R Design Guide 155 Figure 91. GMCH Power Plane Decoupling 6.4.5. Ground Flood Planes To further decouple th

Intel® 810E2 Chipset Platform R 156 Design Guide 6.5. Power_Supply PS_ON Considerations If a pulse on SLP_S3# or SLP_S5# is short enough (~ 10

Intel® 810E2 Chipset Platform R Design Guide 157 7. Design Checklist 7.1. Design Review Checklist This checklist highlights design considera

Intel® 810E2 Chipset Platform R 158 Design Guide Table 42. AGTL+ Connectivity Checklist for 370-Pin Socket Processors Processor Pin I/O Rec

Intel® 810E2 Chipset Platform R Design Guide 159 Table 43. CMOS Connectivity Checklist for 370-Pin Socket Processors Processor Pin I/O Reco

Intel® 810E2 Chipset Platform R 16 Design Guide Term Definition Pad A feature of a semiconductor die contained within an internal logic pac

Intel® 810E2 Chipset Platform R 160 Design Guide Table 45. Miscellaneous Checklist for 370-Pin Socket Processors Processor Pin I/O Recomme

Intel® 810E2 Chipset Platform R Design Guide 161 Processor Pin I/O Recommendations VREF[7:0] I Connect to Vref voltage divider made up of 7

Intel® 810E2 Chipset Platform R 162 Design Guide Checklist Line Items Comments LMD[27:31] Reset strapping options: Strapping options: For a “1

Intel® 810E2 Chipset Platform R Design Guide 163 7.2. Intel® ICH2 Checklist 7.2.1. PCI Interface Checklist Items Recommendations All All in

Intel® 810E2 Chipset Platform R 164 Design Guide Checklist Items Recommendations Comments 5 Max mismatch between the length of a clock trace a

Intel® 810E2 Chipset Platform R Design Guide 165 Checklist Items Recommendations Comments 23 LAN_CLK Connect to LAN_CLK on Platform LAN Connect

Intel® 810E2 Chipset Platform R 166 Design Guide Checklist Items Recommendations PIRQ[G:F]#/ GPIO[4:3] These signals require a pull-up resistor

Intel® 810E2 Chipset Platform R Design Guide 167 7.2.8. USB Checklist Items Recommendations USBP[3:0]P USBP[3:0]N See Figure 92 for circuitr

Intel® 810E2 Chipset Platform R 168 Design Guide 7.2.9. Power Management Checklist Items Recommendations THRM# Connect to temperature Sensor

Intel® 810E2 Chipset Platform R Design Guide 169 7.2.11. System Management Checklist Items Recommendations SMBDATA SMBCLK Requires external p

Intel® 810E2 Chipset Platform R Design Guide 17 1.1.1. References • Intel® 810E Chipset: 82810E Graphics and Memory Controller Hub (GMCH) Data

Intel® 810E2 Chipset Platform R 170 Design Guide 7.2.14. AC’97 Checklist Items Recommendations AC_BITCLK No extra pull-down resistors requir

Intel® 810E2 Chipset Platform R Design Guide 171 Figure 93. SPKR Circuitry Speaker_CircuitStuff jumper todisable time-outfeature.R < 7.3 kΩR

Intel® 810E2 Chipset Platform R 172 Design Guide 7.2.16. Power Checklist Items Recommendations V_CPU_IO[1:0] The power pins should be conne

Intel® 810E2 Chipset Platform R Design Guide 173 7.2.17. IDE Checklist Checklist Items Recommendations PDD[15:0], SDD[15:0] No extra series t

Intel® 810E2 Chipset Platform R 174 Design Guide Figure 95. Host/Device Side Detection Circuitry 80-conductorIDE cableIDE drive5 VICH2GPIOGPI

Intel® 810E2 Chipset Platform R Design Guide 175 7.3. LPC Checklist Checklist Items Recommendations RCIN# Pull up through 8.2-kΩ resistor t

Intel® 810E2 Chipset Platform R 176 Design Guide 7.4. System Checklist Checklist Items Recommendations KEYLOCK# Pull up through 10-kΩ resist

Intel® 810E2 Chipset Platform R Design Guide 177 7.6. Clock Synthesizer Checklist Checklist Items Recommendations REFCLK Connects to R-Re

Intel® 810E2 Chipset Platform R 178 Design Guide 7.7. ITP Probe Checklist Checklist Items Recommendations R_TCK, TCK R_TMS, TMS Connect t

Intel® 810E2 Chipset Platform R Design Guide 179 8. Flexible Motherboard Guidelines 8.1. Flexible Processor Guidelines 8.1.1. Flexible Syste

Intel® 810E2 Chipset Platform R 18 Design Guide 1.2. System Overview The 810E2 chipset enhances the performance of the first generation Integra

Intel® 810E2 Chipset Platform R 180 Design Guide Table 50. Flexible Processor Voltage and Current Guidelines for 2.0 V Processors 1 Symbol Pa

Intel® 810E2 Chipset Platform R Design Guide 181 8.1.2. System Bus AC Guidelines Table 51 and Table 52 contain 66 MHz and 100 MHz system bus A

Intel® 810E2 Chipset Platform R 182 Design Guide Figure 97. BCLK Waveform 761a2.0V1.25V0.5VtrtptfthtlCLKTr= T5 (Rise Time)Tf= T6 (Fall Time)T

Intel® 810E2 Chipset Platform R Design Guide 183 Figure 98. Processor System Bus Valid Delay Timings CLKSignal000762bTxTxTpwV Valid ValidTxT7

Intel® 810E2 Chipset Platform R 184 Design Guide 8.1.3. Thermal Guidelines The following table provides the recommended thermal design power di

Intel® 810E2 Chipset Platform R Design Guide 185 9. Third-Party Vendor Information This design guide has been compiled to give an overview of

Intel® 810E2 Chipset Platform R 186 Design Guide Table 58. Flat Panel Vendors Contact Phone Silicon Images Inc John Nelson 408-873-3111

Intel® 810E2 Chipset Platform R Design Guide 187 Table 61. TV Encoders Vendors Component Contact Phone Chrontel CH7007 / CH7008 Chi Tai Hon

Intel® 810E2 Chipset Platform R 188 Design Guide This page is intentionally left blank.

Intel® 810E2 Chipset Platform R Design Guide 189 Appendix A: Intel® 810E2 Chipset Platform Reference Schematics This appendix provides a set of

Intel® 810E2 Chipset Platform R Design Guide 19 1.2.1. Graphics and Memory Controller Hub (GMCH) The GMCH provides the interconnect between th

AAA AINTEL® PENTIUM® III & INTEL® CELERON (TM)PROCESSOR (PGA370) / INTEL® 810E2 CHIPSETUNIPROCESSOR CUSTOMER REFERENCE SCHEMATICSREVISION 1.0Tit

AAA ADATACTRLADDRTermVRMICH2KeyboardMouseFloppy ParallelSerial 1SIOClockPCI CONN 1PCI CONN 2PCI CONN 3Block Diagram2 DIMMModulesUSB Port 1-4CNRCONNECT

AAA A370 - Pin Socket Part 1Intel® 810e2 Chipset Customer Reference Board370-PIN SOCKET PART 1341.010/24/003IAMG Platform Apps Engineering1900 Prairie

11A AFSB66M100M133Mrsvdnear VCMOS Processor PinVCMOS Decouping370 - Pin SocketPlace 0603 PaclagePart2Place Site w/in 0.5"Do Not stuff Cof clock p

5544332211D DC CB BA AAGTL Termination" One Cap for each 2 R-Pack "HEATSINK GROUNDINGIntel® 810e2 Chipset Customer Reference BoardAGTL TERMI

AAA AClock Synthesizer- Place all decoupling caps as close to VCC/GND pins as possibleNotes:Minimize Stub Length fromCLK14 trace toJP20A.- PCI_0/ICH p

AAA A82810E, PART 1: HOST INTERFACEPlace site w/in 0.5"of clock ball (V6)Do not Stuff C365AIntel® 810e2 Chipset Customer Reference Board82810E, P

AAA A82810E, PART 2: SYSTEM MEMORYAND HUB INTERFACEas possible to GMCHPlace Resistor as ClosePlace C369A as closeas possible to GMCHPlace HUBREF Gener

AAA APlace as close asPossible to GMCHand via straight toVSS plane.GMCH RESET STRAPSPlace R242A within 0.5"of the GMCH Ball.Use Surface Mount Cap

AAA A4MB DisplayCacheIntel® 810e2 Chipset Customer Reference BoardDisplay Cache341.010/24/0010IAMG Platform Apps Engineering1900 Prairie City RoadFols

Intel® 810E2 Chipset Platform R 2 Design Guide INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL PRODUCTS. NO LICENSE, EXPRE

Intel® 810E2 Chipset Platform R 20 Design Guide 1.2.3. System Configurations Figure 1. Intel® 810E2 Chipset System System Bus (66/100/133 MHz)S

AAA ASYSTEM MEMORYIntel® 810e2 Chipset Customer Reference BoardSystem Memory : DIMM0341.010/24/0011IAMG Platform Apps Engineering1900 Prairie City Roa

AAA ASYSTEM MEMORYIntel® 810e2 Chipset Customer Reference BoardSystem Memory : DIMM1341.010/24/0012IAMG Platform Apps Engineering1900 Prairie City Roa

AAA APlace Rwithin 0.5"of HLCOMPpin via a10 mil widetracePlace as close asPossible to ICH2and via straightto VSS planeNPOPICH2 Part 1Intel® 810e2

AABBCCDDEE4 43 32 21 1ICH2 Part 2Intel® 810e2 Chipset Customer Reference BoardICH2 Part 2341.010/24/0014IAMG Platform Apps Engineering1900 Prairie Cit

8877665544332211D DC CB BA AIDEFWHIntel® 810e2 Chipset Customer Reference BoardFWH & ULTRA-ATA100 IDE connectors341.010/24/0015IAMG Platform Apps

8877665544332211D DC CB BA AW83627HFFDD Signals Trace 8 or 10 milIntel® 810e2 Chipset Customer Reference BoardSuper I/O & FDC341.010/24/0016IAMG P

AABBCCDDEE4 43 32 21 1Intel® 810e2 Chipset Customer Reference BoardPCI 1 & 2341.010/24/0017IAMG Platform Apps Engineering1900 Prairie City RoadFol

AABBCCDDEE4 43 32 21 1Intel® 810e2 Chipset Customer Reference BoardPCI 3 & 4341.010/24/0018IAMG Platform Apps Engineering1900 Prairie City RoadFol

8877665544332211D DC CB BA AJP4 Pin 1 near USB2 Pin 3JP4 Pin 2 near USB2 Pin 5JP5 Pin 1 near USB2 Pin 4JP5 Pin 2 near USB2 Pin 6Intel® 810e2 Chips

AAA AAC'97CODEC"SINGLE POINT CONNECTION"Intel® 810e2 Chipset Customer Reference BoardAC97 CODEC341.010/24/0020IAMG Platform Apps Engine

Intel® 810E2 Chipset Platform R Design Guide 21 1.3. Platform Initiatives 1.3.1. Hub Interface As I/O speeds increase, the demand placed on the

8877665544332211D DC CB BA ACD Analog InputLine_In Analog InputMicrophone InputStereo HP/Spkr out"SINGLE POINT CONNECTION"Intel® 810e2 Chips

AABBCCDDEE4 43 32 21 1Parallel PortWAKE ON MODEMCOM1COM2WAKE ON LANIntel® 810e2 Chipset Customer Reference BoardWOL, WOR & 2S1P341.010/24/0022IAMG

AABBCCDDEE4 43 32 21 1Game PortKeyboardMouseIRIntel® 810e2 Chipset Customer Reference BoardKybrd / Mse / F. Disk / Gme Connectors341.010/24/0023IAMG P

AAA ADo Not StuffDigital Video OutPlace C106Anear U8A pin 3Intel® 810e2 Chipset Customer Reference BoardDigital Video Out341.010/24/0024IAMG Platform

AAA AProtection Circuitfor 20V Tolerance20 Pin Flat Panel Connectoris also populated.Populate if DFP DeviceDe -BounceCircuitBLM11B750S is rated at70Oh

8877665544332211D DC CB BA AHDD LEDPWR_SWKEYLOCKSMI_SWSPEAKERRESETGREEN LEDRESERVETRADITIONAL PC SOUND3-4 ON1-2 ONMIXED IN ON_BOARD AC97 CODECJP2ON BO

AABBCCDDEE4 43 32 21 1Do not stuff. Forde bug onlyResume Reset Circuitry. 22msec delayIntel® 810e2 Chipset Customer Reference BoardATX Power341.010/

AABBCCDDEE4 43 32 21 1CPU FANCHASSIS FANPWR FANTemperature SensingIf case is opened,this switch should be closed.Voltage Sensing"power use"&

AABBCCDDEE4 43 32 21 1TO-252TO-252TO-252TO-263TO-263"SINGLE POINTCONNECTIONIntel® 810e2 Chipset Customer Reference BoardVoltage Regulators Part 1

AABBCCDDEE4 43 32 21 1Intel® 810e2 Chipset Customer Reference BoardVoltage Regulators Part 2341.010/24/0030IAMG Platform Apps Engineering1900 Prairie

Intel® 810E2 Chipset Platform R 22 Design Guide 1.3.7. Firmware Hub (FWH) Flash BIOS The 810E2 chipset platform supports firmware hub BIOS mem

AABBCCDDEE4 43 32 21 1SW1:5OFF FORCE CPU FREQ STRAP TO SAFE MODE(1111)USE CPU FREQ STRAP IN ICH REGISTERAC_SDOUTONSTRAP(SPKR)OFF REBOOT ON 2ND WATCHDO

AABBCCDDEE4 43 32 21 1PCI ICHDo not populateCPUIntel® 810e2 Chipset Customer Reference BoardPullup Resistors341.010/24/0032IAMG Platform Apps Engineer

AAA AUNUSED GATESIntel® 810e2 Chipset Customer Reference BoardUnused Gates341.010/24/0033IAMG Platform Apps Engineering1900 Prairie City RoadFolsom, C

AABBCCDDEE4 43 32 21 1" GMCH : 0.1U//0.01U at each conner and each side-center "" GMCH : Near Display Cache Quadrant "" Di

Intel® 810E2 Chipset Platform R Design Guide 23 AC97_connectionsICH2360 EBGAAC’97ModemCODECModem PortAudio PortAC’97 DigitalLinkAC’97Audio/CODE

Intel® 810E2 Chipset Platform R 24 Design Guide 1.3.9. Low Pin Count (LPC) Interface In the 810E2 chipset platform, the Super I/O (SIO) compon

Intel® 810E2 Chipset Platform R Design Guide 25 2. PGA370 Processor Design Guidelines This chapter provides PGA370 processor design guidelines

Intel® 810E2 Chipset Platform R 26 Design Guide Table 1. Platform Pin Definition Comparison for Single Processor Designs Pin # Legacy PGA37

Intel® 810E2 Chipset Platform R Design Guide 27 2.2.1. Layout Guidelines for Intel® Pentium® III Processors The following layout guide support

Intel® 810E2 Chipset Platform R 28 Design Guide Table 3. Example TFLT_MIN Calculations for 133 MHz Bus1 Driver Receiver Clk Period2 TCO_MAX TS

Intel® 810E2 Chipset Platform R Design Guide 29 Figure 2. Topology for 370-Pin Socket Designs with Single-Ended Termination (SET) 370pin_set.

Intel® 810E2 Chipset Platform R Design Guide 3 Contents 1. Introduction ...

Intel® 810E2 Chipset Platform R 30 Design Guide 2.2.2.1. Motherboard Layout Rules for AGTL+ Signals Minimizing Crosstalk The following general

Intel® 810E2 Chipset Platform R Design Guide 31 Table 7. Routing Guidelines for Non-AGTL+ Signals Signal Trace Width Spacing to Other Trace

Intel® 810E2 Chipset Platform R 32 Design Guide 2.2.2.4. Additional Considerations • Distribute VTT with a wide trace. A 0.050” minimum trace

Intel® 810E2 Chipset Platform R Design Guide 33 Figure 4. BSEL[1:0] Circuit Implementation for PGA370 Designs SBus_FreqSel_pga370.vsd82810E G

Intel® 810E2 Chipset Platform R 34 Design Guide 2.2.5. CLKREF Circuit Implementation The CLKREF input requires a 1.25V source. It can be gen

Intel® 810E2 Chipset Platform R Design Guide 35 2.2.7. Connecting RESET# and RESET2# on a Flexible PGA370 Design The 810E2 chipset platform de

Intel® 810E2 Chipset Platform R 36 Design Guide 2.2.8.1. Power-Up/Reset Strap Options Table 10 lists power-up options that are loaded into th

Intel® 810E2 Chipset Platform R Design Guide 37 2.2.10.1. VCCcore Decoupling Design • Ten or more 4.7 µF capacitors in 1206 packages. All cap

Intel® 810E2 Chipset Platform R 38 Design Guide 2.2.11. Thermal/EMI Differences Heatsink requirements will be different for FC-PGA processors f

Intel® 810E2 Chipset Platform R Design Guide 39 2.2.13. PGA370 Socket Connector Strapping Option Clarifications of the keep-out zone changes a

Intel® 810E2 Chipset Platform R 4 Design Guide 3.1.1 System Memory Routing Example ...

Intel® 810E2 Chipset Platform R 40 Design Guide This page is intentionally left blank.

Intel® 810E2 Chipset Platform R Design Guide 41 3. Layout and Routing Guidelines This chapter describes motherboard layout and routing guideli

Intel® 810E2 Chipset Platform R 42 Design Guide Figure 10. Nominal Board Stackup Component Side Layer 1 (1/2 oz. cu)Power Plane Layer 2 (1 oz.

Intel® 810E2 Chipset Platform R Design Guide 43 Figure 12. Intel® ICH2 Quadrant Layout (Top View) IDESM busAC'97LANHub interface Processo

Intel® 810E2 Chipset Platform R 44 Design Guide Figure 13. Firmware Hub (FWH) Packages pck_fwh.vsd1234567891011121314151617181920403938373635

Intel® 810E2 Chipset Platform R Design Guide 45 3.3. Intel® 810E2 Chipset Component Placement The assumptions for component placement are: • u

Intel® 810E2 Chipset Platform R 46 Design Guide 3.4. System Memory Layout Guidelines 3.4.1. System Memory Solution Space Figure 15. System Me

Intel® 810E2 Chipset Platform R Design Guide 47 3.1.1 System Memory Routing Example Figure 16. System Memory Routing Example

Intel® 810E2 Chipset Platform R 48 Design Guide 3.4.2. System Memory Connectivity Figure 17. System Memory Connectivity SCS[3:2]#SCS[1:0]#SC

Intel® 810E2 Chipset Platform R Design Guide 49 3.5. Display Cache Interface Figure 18. Display Cache (Topology 1) A1Mx16 3.5.1. Display Cach

Intel® 810E2 Chipset Platform R Design Guide 5 3.21.2.2. Power and Ground Connections ... 85

Intel® 810E2 Chipset Platform R 50 Design Guide Figure 20. Display Cache (Topology 3) 1Mx161Mx16DEFF22 Ohms Table 15. Display Cache Routing

Intel® 810E2 Chipset Platform R Design Guide 51 3.6. Hub Interface The 810E2 chipset’s GMCH ball assignment and ICH2 ball assignment have been

Intel® 810E2 Chipset Platform R 52 Design Guide 3.6.2. Strobe Signals Due to their differential nature, the hub interface strobe signals should

Intel® 810E2 Chipset Platform R Design Guide 53 Figure 23. Single Hub Interface Reference Divider Circuit HUBREFHUBREFGMCHICHHubRef1300 Ω1.8V

Intel® 810E2 Chipset Platform R 54 Design Guide 3.7. Intel® ICH2 3.7.1. Decoupling The ICH2 is capable of generating large current swings when

Intel® 810E2 Chipset Platform R Design Guide 55 Figure 25. Intel® ICH2 Decoupling Capacitor Layout 3.3V Core1.8V Core1.8V Standby3.3V Standby3.

Intel® 810E2 Chipset Platform R 56 Design Guide The following figure shows an example power-on sequencing circuit that ensures the “2V Rule” is

Intel® 810E2 Chipset Platform R Design Guide 57 3.9. Power Plane Splits Figure 27. Power Plane Split Example pwr_plane_splits 3.10. Thermal D

Intel® 810E2 Chipset Platform R 58 Design Guide 3.11.1. Cabling • Length of cable: Each IDE cable must be equal to or less than 18”. • Capaci

Intel® 810E2 Chipset Platform R Design Guide 59 Figure 28. Combination Host-Side / Device-Side IDE Cable Detection 80-conductorIDE cableIDE dri

Intel® 810E2 Chipset Platform R 6 Design Guide 4.1.6.3. Flight Time Hardware Validation ...123

Intel® 810E2 Chipset Platform R 60 Design Guide 3.12.2. Device-Side Cable Detection For platforms that must implement device-side detection on

Intel® 810E2 Chipset Platform R Design Guide 61 3.12.3. Primary IDE Connector Requirements Figure 30. Connection Requirements for Primary ID

Intel® 810E2 Chipset Platform R 62 Design Guide 3.12.4. Secondary IDE Connector Requirements Figure 31. Connection Requirements for Secondar

Intel® 810E2 Chipset Platform R Design Guide 63 3.13. AC’97 The ICH2 implements an AC’97 2.1-compliant digital controller. Any codec attached t

Intel® 810E2 Chipset Platform R 64 Design Guide Clocking is provided from the primary codec on the link via BITCLK, and it is derived from a 24

Intel® 810E2 Chipset Platform R Design Guide 65 As shown in the following figure, when a single codec is located on the motherboard, the resist

Intel® 810E2 Chipset Platform R 66 Design Guide Figure 34. CDC_DN_ENAB# Support Circuitry for Multi-Channel Audio Upgrade PrimaryAudioCodecRES

Intel® 810E2 Chipset Platform R Design Guide 67 The following figure shows the case of two-codecs down and a dual-codec CNR. In this case, both

Intel® 810E2 Chipset Platform R 68 Design Guide 3.13.1.1. Valid Codec Configurations Table 20. Codec Configurations Valid Codec Configurations

Intel® 810E2 Chipset Platform R Design Guide 69 3.14. CNR The Communication and Networking Riser (CNR) Specification defines a hardware-scalabl

Intel® 810E2 Chipset Platform R Design Guide 7 7.2.6. Interrupt Interface ...

Intel® 810E2 Chipset Platform R 70 Design Guide impedance of both wires, resulting in an individual wire presenting a 45-Ω impedance. The trace

Intel® 810E2 Chipset Platform R Design Guide 71 3.16. ISA Implementations that require ISA support can benefit from the enhancements of the IC

Intel® 810E2 Chipset Platform R 72 Design Guide Figure 39. SMBus/SMLink Interface 82801BAHost Controller andSlave InterfaceSMBusSMBCLKSPD DataT

Intel® 810E2 Chipset Platform R Design Guide 73 3.19. PCI The ICH2 provides a PCI Bus interface compliant with the PCI Local Bus Specification,

Intel® 810E2 Chipset Platform R 74 Design Guide 3.20.1. RTC Crystal The ICH2 RTC module requires an external oscillating source of 32.768 kHz c

Intel® 810E2 Chipset Platform R Design Guide 75 3.20.2. External Capacitors To maintain RTC accuracy, the external capacitor C1 must be 0.047 µ

Intel® 810E2 Chipset Platform R 76 Design Guide Figure 42. Diode Circuit to Connect RTC External Battery VCC3_3SBYVccRTC1.0 µF1 kΩRTC_ext_bat

Intel® 810E2 Chipset Platform R Design Guide 77 The ICH2 RTC requires some additional external circuitry. The RTCRST# signal is used to reset t

Intel® 810E2 Chipset Platform R 78 Design Guide Figure 44. RTC Power-well Isolation Control RSMRST#ICH2from Glue Chipor other sourceRSMRST#2.2

Intel® 810E2 Chipset Platform R Design Guide 79 3.21. LAN Layout Guidelines The ICH2 provides several options for integrated LAN capability.

Intel® 810E2 Chipset Platform R 8 Design Guide Figures Figure 1. Intel® 810E2 Chipset System ...

Intel® 810E2 Chipset Platform R 80 Design Guide Table 22. LAN Design Guide Section Reference Layout Section Figure Ref. Design Guide Sectio

Intel® 810E2 Chipset Platform R Design Guide 81 3.21.1.2. Point-to-Point Interconnect The following guidelines are for a single-solution mothe

Intel® 810E2 Chipset Platform R 82 Design Guide Table 24. LOM/CNR Length Requirements Configuration A B C D Intel® 82562EH 0.5” to 6.0” 4.

Intel® 810E2 Chipset Platform R Design Guide 83 3.21.1.5. Crosstalk Consideration Noise due to crosstalk must be carefully minimized. Crosstalk

Intel® 810E2 Chipset Platform R 84 Design Guide Figure 49. Trace Routing 45 degreesTrace45degrees Trace Geometry and Length The key factors in

Intel® 810E2 Chipset Platform R Design Guide 85 3.21.2.2. Power and Ground Connections Comply with the following rules and guidelines for powe

Intel® 810E2 Chipset Platform R 86 Design Guide Comply with the following rules to help reduce circuit inductance in both backplanes and mother

Intel® 810E2 Chipset Platform R Design Guide 87 3.21.2.4. Common Physical Layout Issues Common physical layer design and layout mistakes in LA

Intel® 810E2 Chipset Platform R 88 Design Guide to ground. Using capacitors with capacitances exceeding a few pF in either of these locations c

Intel® 810E2 Chipset Platform R Design Guide 89 3.21.3.2. Guidelines for Intel® 82562EH Component Placement Component placement can affect the

Intel® 810E2 Chipset Platform R Design Guide 9 Figure 51. Intel® 82562EH Termination ...

Intel® 810E2 Chipset Platform R 90 Design Guide Figure 51. Intel® 82562EH Termination 123456TabTab123456TabTab8Phone / modemShield groundLine

Intel® 810E2 Chipset Platform R Design Guide 91 3.21.3.5. Critical Dimensions There are three dimensions to consider during layout. Distance ‘B

Intel® 810E2 Chipset Platform R 92 Design Guide Distance from Intel® 82562EH to Magnetics Module Due to the high speed of signals present, dist

Intel® 810E2 Chipset Platform R Design Guide 93 3.21.4.2. Crystals and Oscillators To minimize the effects of EMI, clock sources should not be

Intel® 810E2 Chipset Platform R 94 Design Guide 3.21.4.4. Critical Dimensions There are two dimensions to consider during layout. Distance ‘B’

Intel® 810E2 Chipset Platform R Design Guide 95 Distance from Intel® 82562ET to Magnetics Module Distance B should also be designed to be less

Intel® 810E2 Chipset Platform R 96 Design Guide Figure 55. Termination Plane N/CRJ-45Magnetics ModuleRDPRDNTDPTDNTermination PlaneAdditional ca

Intel® 810E2 Chipset Platform R Design Guide 97 There are four pins which are used to put the 82562ET/EM controller in different operating stat

Intel® 810E2 Chipset Platform R 98 Design Guide Figure 58. Dual-Footprint Analog Interface dual_ft_AN_connMagneticsModuleTDPRJ4582562EH/82562ET

Intel® 810E2 Chipset Platform R Design Guide 99 3.22. LPC/FWH The following provides general guidelines for compatibility and design recommenda